Recent DDR-based system memory interface per-pin speeds are approaching 1.6 GHz (3.2 Gbps) with sDDR4. One bottleneck limiting this frequency target is command timing, since it employs a single driver to perform multiple loads. FIG. 1 illustrates this issue. As FIG. 1 shows, a single driver 110 is tasked with driving signals to four separate loads 120a, 120b, 120c, 120d. The driver 110 experiences timing margin losses by virtue of numerous reflections from the four loads.
To achieve the required speed target, sDDR4 introduces a half-rate, 2N timing mode (also called a gear-down mode) that may be employed for the command interface (hence making the full rate a 1N timing mode). FIG. 2 depicts control signals for both the 1N and 2N timing modes. The 2N mode appears to alleviate the bottleneck limiting the sDDR4 frequency target.